1. Field
Various embodiments of the present invention relate to a flash memory system and, more particularly, to a flash memory system performing error correction with a concatenated Bose-Chadhuri-Hocquenghem (concatenated BCH) code and an operation method thereof.
2. Description of the Related Art
With the Increase in speed of processors and main storage devices, such as RAM, a bottleneck has occurred in various electronic devices. The bottleneck is due to processors and main storage devices being limited by the operating speed of the auxiliary storage devices. Devices that store data using a magnetic field, such as hard disk drives (HDDs), and optic disc drives (ODDs), such as CDs and DVDs, have generally been used for auxiliary storage devices. The speed at which optical disc devices may operate is limited, and often slow relative to processor and main memory speeds. Devices that store data using magnetic fields generally operate at higher speeds than optical disc devices, but still cause bottlenecking, and are prone to damage from physical impacts. Accordingly, solid-state drives (SSDs) formed using semiconductor elements may be a solution to alleviate the bottlenecking problem. SSDs have processing speeds higher than HDDs, and may input and output data at high speed without requiring time to search for data that needs to be randomly accessed. In addition, since SSDs have no moving parts, there are no mechanical delays or mechanical failures and the likelihood of damage from physical impact is significantly reduced. Further, SSDs are energy efficient, do not generate a lot of heat, and are quiet. Additionally, SSDs have a small form factor and relative to HDDs, making them ideal for portable electronic devices.
In SSDs, generally NOR flash memory or NAND flash memory is used. NAND flash memory is capable of being highly integrated and has serial connections, making it suitable for high capacity memory devices, and has high read/writing speeds. Therefore, NAND flash memory is used for most mass capacity SSD.
However, the NAND flash memory element is constantly undergoing miniaturization and it is increasingly being required to store multiple bits of Information per memory cell. The increased storage density results in adverse effects such as deteriorated reliability and decreased life.
Referring to FIG. 1, the likelihood of errors caused by inter-level interference increases during reading operations when there is an increase in the number of bits stored per cell, and the error occurrence drastically increases as reading/writing operations are repeated, resulting in decreased reliability of the product overall. Therefore, an error correction circuit that is both energy efficient and has high processing power is an essential element in designing stable NAND flash memories at reasonable prices.
To resolve such concerns, error correction encoding is generally used. Error correction encoding requires extra bits of data storage to store information for error detection and correction. This requires chip area for extra memory cells to store the extra bits. However, to maximize the storage capacity of the storage medium, the area used to store the extra bits is miniaturized, and the amount extra bits required needs to be minimized as well.
In addition, due to the increase of data storage errors, advanced error correction encoding has been substituted for conventional BCH encoding and Reed-Solomon (RS) encoding. This advanced error correction encoding requires exponentially greater complexity and greater data storage.
A low density parity check (LDPC) code that is proven to have good performance in the field of telecommunication may be one of the candidates. However, the LDPC code is not widely commercialized due to the complexity of the decoder, since the information that a flash memory provides to an error correction decoder is mainly hard decision information.
Therefore, to improve the performance of the LDPC code, information similar to soft decision information needs to be generated by raising a quantization level of the hard decision information, for example, by re-reading a page where errors occur with changed threshold voltage for the page.
A block-wise concatenated BCH (BC-BCH) code has excellent error correction performance with hard decision information, and the BC-BCH code decoder is less complex and more easily implemented than conventional BCH code decoders.
The conventional BC-BCH code decoding techniques may include iteratively decoding a row BCH constituent code and a column BCH constituent code in an alternate way when only the hard decision information is given, and lowering an error floor through reconstruction of information by utilizing the chase decoding for the decoding-failed BCH constituent code when the soft decision information is given. That is, the soft decoding technique where the row BCH constituent code and the column BCH constituent code cooperate with each other in decoding when using the soft decision information, which improves the error floor characteristics and the overall decoding performance, is not proposed. Also, unlike the conventional product code, a result of the hard decision decoding may be used for the soft decision decoding. However, the BC-BCH code decoding techniques utilizing the result of the hard decision decoding for the soft decision decoding have not been implemented.
When the hard decision decoding fails, the BC-BCH code has information for decoding-failed BCH constituent codes, which causes the failure of the hard decision decoding. Therefore, the BC-BCH code has an advantage of locating the decoding-failed BCH constituent codes when the hard decision decoding fails.
Accordingly, the conventional arts may effectively lower the error floor of the BC-BCH by re-reading information having the error from the memory cell (read and retry) and performing the chase decoding. However, according to the conventional arts, the soft decision information is used only for lowering the error floor while the performance of the BC-BCH code may not be improved.